Four Validation Bottlenecks.
One Path to TRL 6-7.
VENDOR engineers identify the four architectural points where real-world operational function must prove itself — as the honest precondition for transition to independent verification at TRL 6-7.
VENDOR.Max is an Armstrong-type nonlinear electrodynamic oscillator at TRL 5-6 laboratory validation stage. This document is engineering self-disclosure by the VENDOR co-founders of the four architectural stress points where real-world operation must be proven before transition to TRL 6-7 formal verification. Validation differs from verification and certification. Energy conservation at the device boundary is the governing constraint, not a validation parameter. What requires validation is operational function at four specific points — described below.
Validation Is Not Verification.
Verification Is Not Certification.
Three words commonly conflated in deep-tech communication carry three different technical meanings. This document covers the first. The other two have their own documents, referenced below. The distinction is not rhetorical — it determines what is measured, by whom, with what methodology, and for what purpose.
Validation
- Does it operationally function under real-load conditions?Engineering question
- Extended operational testing under load envelope representative of deployed conditions.Method
- Engineering team + real operational exposure (extended cycles, variable load).Performed by
- Engineering confidence that the architecture performs as designed under real-world stress.Output
- Transition from TRL 5-6 to TRL 6-7.TRL scope
Verification
- What exactly, numerically, crosses each defined measurement boundary?Engineering question
- Instrumented metrology under controlled laboratory conditions, with calibrated instruments, traceable to standards.Method
- Accredited laboratory under documented protocol.Performed by
- Metrologically precise measurement of defined quantities at defined boundaries.Output
- Formal TRL 6-7 transition.TRL scope
- Full protocolReference
Certification
- Does the product comply with specific regulatory safety and performance standards?Engineering question
- Formal conformity assessment against CE / UL / ISO / IEC standards by notified body.Method
- Accredited certification body (TÜV, Intertek, DNV).Performed by
- Certification mark permitting market deployment.Output
- TRL 7-8 transition.TRL scope
- Pathway · StandardsReference
Validation precedes verification. Verification precedes certification. Skipping any step produces documents that look rigorous but measure the wrong thing. What follows is an honest engineering map of where VENDOR.Max stands in the first of these three stages.
How VENDOR.Max Operates —
and Where Real-World Proof Is Still Required
VENDOR.Max operation proceeds in six steps. The first two are classical processes validated at component level and well established in standard physics. The subsequent four are architectural points where real-world operation under extended load must prove itself before formal verification can apply. We describe all six below, and we name the four openly — because only engineers who built the system can accurately identify where it needs to prove itself.
Startup impulse charges storage capacitors
Status: ValidatedAn external electrical supply through Port (1) charges the storage capacitors (C2.1, C2.2, C2.3) to a voltage above the breakdown threshold of at least one discharger in the Arrester unit.
This is a classical capacitor-charging process. It is validated at component level by standard electrical testing. It is not under validation scrutiny in this document.
Pre-breakdown field forms across the Arrester unit
Status: ValidatedThe voltage on the storage capacitors establishes an electric field across the gaps of the parallel dischargers in the Arrester unit. This is classical electrostatics: voltage, gap geometry, dielectric conditions. The field is predictable, computable, and measurable.
This is not under validation scrutiny in this document.
Arrester unit breakdown sequence initiates discharge
Validation Bottleneck #1The Arrester unit contains three parallel dischargers with different breakdown voltages and overlapping-but-shifted frequency spectra. Discharge events initiate current pulses into the primary resonant circuit.
Validation question: What is the degradation rate of the dischargers under extended real-load operation, across the full envelope of expected operating conditions?
This is validation bottleneck #1. Described in detail in Section 4.
Field formation in primary resonant circuit at 2.45 MHz
Validation Bottleneck #2The discharge pulses excite the primary resonant circuit formed by the primary winding (4) and resonant capacitor (6), with target operation at 2.45 MHz. The three parallel dischargers, through overlapping-but-shifted spectra, produce cumulative spectral density at the resonant frequency.
Validation question: Does the cumulative spectral density translate into sufficient field intensity for stable regime formation under extended real-load — not only under ideal bench conditions?
This is validation bottleneck #2. Described in detail in Section 4.
Energy transfer through the primary winding to the secondary resonant structure
Validation Bottleneck #3The primary winding (4) transfers electromagnetic field energy through coupling to the secondary winding (7) and tertiary winding (10), each with its own resonant capacitor — capacitor (8) and capacitor (11), respectively.
Validation question: What energy arrives at the secondary and tertiary resonant structures under extended real-load operation? This must be determined without disclosure of the specific engineering realization of the primary winding, which is protected as know-how at TRL 5-6.
This is validation bottleneck #3. Described in detail in Section 4.
Simultaneous extraction: feedback path AND load path
Validation Bottleneck #4 · CentralThe secondary winding (7), through rectifiers (17, 18, 19), returns energy to the storage capacitors (C2.1, C2.2, C2.3) — this is the regulated feedback path maintaining the operating regime. The tertiary winding (10), through the diode bridge (12), delivers energy to the external load.
Both extractions occur from the same primary electromagnetic field, simultaneously, under operational load.
Validation question: Can the feedback path maintain the operating regime while the load path simultaneously delivers rated power, reliably, across extended real-load conditions?
This is validation bottleneck #4 — the central one. Described in detail in Section 4.
Steps 1 and 2 are classical. Steps 3 through 6 are where validation must operate. Each of the four bottlenecks has a specific character, a specific relationship to know-how protection, and a specific methodology for real-load proof. The following section describes each in turn.
What This Document Is Not About
VENDOR.Max is an Armstrong-type nonlinear electrodynamic oscillator. It is not a "free energy" device, not an over-unity system, not a perpetual motion machine, and not a combustion-driven or rotating-machinery power architecture. Energy conservation at the complete device boundary applies without exception: $P_{\mathrm{in,boundary}} = P_{\mathrm{load}} + P_{\mathrm{losses}} + dE/dt$. Air and gas serve as interaction medium for the ionisation process — not as an energy source. The four validation bottlenecks described below concern operational function under real-load conditions, not physics compliance. Physics compliance is not the subject of this document. It is the governing constraint under which validation is performed.
Validation addresses real-world engineering function. It does not address whether the architecture respects conservation laws. The architecture respects them. That is the governing constraint, not a validation parameter.
Four Bottlenecks — In Detail
Each of the four bottlenecks is defined below as a self-contained engineering block. Each block names its object, states its open question, specifies what is disclosed versus protected as know-how, defines the validation approach, and closes with a canonical statement. Blocks can be read in sequence or independently.
Arrester Unit Electrode Integrity Under Extended Real Load
The parallel dischargers of the Arrester unit, under extended real-load operation at 2.45 MHz, across the expected ambient envelope.
How do the dischargers behave over extended real-load operation, regardless of the specific discharger technology employed?
Standard engineering intuition connects "discharge" with "electrode erosion" and therefore with "finite operational lifetime." This is a reasonable first assumption — and it is the kind of assumption that should be tested rather than argued. The patent (ES2950176 / WO2024209235) specifies "dischargers" in the Arrester unit without further internal classification. This is deliberate.
Three parallel dischargers, differing breakdown voltages, overlapping-but-shifted frequency spectra, function within the primary resonant circuit at 2.45 MHz target.
Specific discharger engineering, including internal construction type, electrode geometry, and associated engineering choices.
The patent describes architectural topology. Know-how protects the specific realization that makes the architecture operationally viable. This distinction is standard deep-tech IP practice at TRL 5-6.
Measurement of electrode degradation rate under extended real-load operation, across the expected ambient envelope (humidity, temperature, pressure). The methodology does not depend on assumptions about discharger type. The methodology depends on direct observation of degradation signatures over time under load.
The patent deliberately leaves discharger type unclassified. The validation task is defined empirically so that the answer emerges from measurement, not from assumption about discharger technology. Any prior intuition about electrode behavior under discharge — regardless of its source — is superseded by direct observation of degradation signatures under extended real-load.
Bottleneck #1 tests empirical endurance of the Arrester unit under real load. It does not test any specific discharger technology. Measurement supersedes assumption.
Cumulative Field Intensity at 2.45 MHz Under Spectral-Overlap Operation
The cumulative electromagnetic field intensity at the 2.45 MHz resonant frequency, produced by three parallel dischargers with overlapping-but-shifted spectra, measured at the primary resonant boundary under real-load conditions.
Does the cumulative spectral density produced by the three dischargers deliver sufficient field intensity at the 2.45 MHz resonant frequency to sustain regime formation under extended real-load — not only under ideal bench conditions?
The multi-discharger architecture is one of the specific engineering design choices disclosed in the patent. Its purpose is to broaden the operational envelope: at any moment, at least one discharger maintains effective excitation of the primary resonant circuit, reducing sensitivity to ambient drift. But cumulative spectral density at a specific target frequency depends on coherence between discharge timings, phase alignment across dischargers, and field superposition under real operating conditions — not under ideal synchronization.
- Overlapping frequency spectra from parallel dischargers mathematically produce cumulative density at the target frequency.
- The architectural design (patent) places the target at 2.45 MHz for the primary resonant circuit.
- Laboratory observation has confirmed regime formation under controlled conditions for cumulative operational hours exceeding 1,000 across test configurations.
- Reproducibility of field intensity under varying real-load conditions (not only under ideal bench conditions).
- Field strength stability across operational duration — does the cumulative density remain within the envelope required for regime formation as ambient and load conditions drift within expected deployment ranges?
- Regime initiation reliability across the operational envelope.
Measurement of field intensity at the primary resonant boundary under extended real-load operation, with load variation representative of deployed conditions. This is a boundary measurement of a known quantity — the question is not whether the field exists, but whether its intensity remains reliably sufficient across real operational conditions.
Bottleneck #2 tests whether spectral overlap holds up under real operating conditions. The field exists. The question is whether its intensity remains reliably sufficient across the operational envelope.
Primary Winding Coupling (Black-Box Validation)
The primary winding (4) as part of a patented resonant architecture at 2.45 MHz, treated as a black box for validation purposes. What is measured is energy crossing the coupling boundary into the secondary resonant structure (winding 7 + capacitor 8) and the tertiary resonant structure (winding 10 + capacitor 11), under extended real-load.
What energy crosses the coupling boundary from the primary winding into the secondary and tertiary resonant structures under extended real-load — measured without disclosure of the primary winding's specific engineering realization?
The primary winding (4) is part of a patented resonant architecture. Its function within the three-circuit field-coupled topology is disclosed in the patent: primary resonance with capacitor (6), field coupling to secondary winding (7) and tertiary winding (10), operation at 2.45 MHz target frequency. What is not disclosed — and is specifically protected as know-how at TRL 5-6 — is the primary winding's specific engineering realization. The reason is direct: conventional engineering intuition about typical inductor configurations leads to incorrect coupling estimates for this specific architectural realization. The engineering choice that makes simultaneous dual-extraction operationally viable is exactly what is IP-protected.
Primary winding (4) as part of a resonant circuit with capacitor (6); functional relationship to secondary winding (7) and tertiary winding (10); target operation at 2.45 MHz; role within the three-circuit field-coupled architecture.
The specific engineering realization of the primary winding — its construction, geometry, and coupling parameters.
Only measurements at the coupling boundary of the primary winding are needed to validate the architecture. What matters operationally is what reaches the secondary and tertiary resonant structures — not the internal details of how that transfer is engineered.
Stated directly: the primary winding's engineering realization cannot be validated by opening it. It can be validated by measuring what comes out of both extraction paths under real load. This is the standard methodology for validation of know-how-protected architectures at TRL 5-6.
The primary winding is a black box. The validation targets are (a) what energy reaches the secondary resonant structure (winding 7 + capacitor 8), and (b) what energy reaches the tertiary resonant structure (winding 10 + capacitor 11), simultaneously, under extended real-load.
The patents describe architecture. Know-how protects realization. Validation targets operational outcome at the boundary. All three statements are simultaneously correct — and jointly define the scope of this bottleneck.
Simultaneous Dual-Extraction Sufficiency Under Extended Real Load (The Central Bottleneck)
The two extraction paths operating simultaneously under extended real-load: secondary winding (7) through rectifiers (17, 18, 19) to storage capacitors (C2.1, C2.2, C2.3) as the feedback path, and tertiary winding (10) through diode bridge (12) to external load as the load path.
Can the secondary winding feedback path maintain the operating regime while the tertiary winding simultaneously delivers rated power, under extended real-load conditions?
All other bottlenecks serve this one. Dischargers must endure. Spectral overlap must deliver sufficient field intensity. The primary winding must couple energy into both extraction paths. And then the central question emerges: can the two extraction paths — secondary winding (7) carrying regime-support energy back through rectifiers (17, 18, 19) to storage capacitors (C2.1, C2.2, C2.3), and tertiary winding (10) carrying load-delivery energy through the diode bridge (12) to the external load — operate simultaneously, sufficiently, reliably, across extended real-load?
- 1,000+ cumulative operational hours across multiple test configurations.
- 532-hour continuous cycle at fixed 4 kW resistive load.
- Approximately 3.996 MWh of electrical energy delivered to external load across the 532-hour cycle.
- Regime persistence observed within the tested operating envelope.
- Reproducibility of simultaneous extraction across the full operational envelope expected in deployed conditions (load transients, ambient variation, extended duration beyond current test cycles).
- Absence of trade-off degradation: does the feedback path retain regime support as load demand increases toward rated power? Does the load path retain delivery capacity as feedback demand varies?
- Stability of the simultaneous dual extraction under conditions representative of deployment — not only under controlled bench conditions.
This is the question that ties the whole architecture together. Regime formation is established. Regime persistence under load is observed. What has not yet been proven under the full operational envelope is reliable simultaneous sufficiency — that both extraction paths deliver what each requires, at the same time, across the conditions of real deployment.
All four bottlenecks converge here.
Extended real-load testing across the operational envelope, with documented load variation, extended duration, and explicit reporting of the tested conditions. The measurement boundary is the complete device boundary. The observable quantities are input energy at Port (1), output energy at the load terminals, and regime continuity over the test interval.
What this generates is engineering confidence under real-world operational stress. What follows it is formal metrological verification under controlled instrumentation — a separate document.
Bottleneck #4 tests whether both extraction paths can sustain their respective roles simultaneously under real deployment stress. Regime persistence and load delivery are observed individually. What real-world validation targets is their joint reliability across the full operational envelope.
Why Engineers Must Disclose Their Own Bottlenecks
A document like this — identifying one's own open questions with specificity and using patent-nomenclature terminology without deflection — is unusual in deep-tech public communication. It is worth stating directly why it is appropriate here, at this stage, for this architecture.
Reason 1 — Only the engineers who built the system can accurately identify where it needs to prove itself
Third-party reviewers working from architectural documentation will either miss the specific architectural points where real-load behavior is the open question (creating false confidence) or invent bottlenecks at points already validated at component level (wasting validation effort on already-established processes). Accurate self-assessment by the engineering team is the only reliable source of the actual bottleneck list. The list above is that list. No external review at this stage would independently arrive at these four specific items without this document as starting reference.
Reason 2 — Know-how protection makes self-disclosure of validation bottlenecks the only consistent path
Patents describe architecture. Know-how protects the specific engineering realization that makes the architecture operationally viable. This distinction is normal practice in deep-tech IP strategy and is appropriate at TRL 5-6.
But it creates a specific constraint: if the engineering solution inside a patented architecture is IP-protected, then only the party that knows where the solution sits can identify what external measurements validate its operation — without disclosing the solution itself. Boundary-level validation is the standard methodology for this. Self-disclosure of the bottlenecks is the precondition for boundary-level validation.
Reason 3 — Engineering maturity is demonstrated by accurate self-assessment, not by claims of completeness
Teams that claim everything is validated are not credible at TRL 5-6. Teams that identify their own specific bottlenecks — with precision, using patent-nomenclature terminology, without deflection or narrative softening — demonstrate the kind of engineering discipline that is the basis for meaningful subsequent engagement with TÜV, DNV, Intertek, and other institutional verifiers. Naming the four bottlenecks here is a deliberate signal: this team knows what remains to be proven.
We name four bottlenecks because these are the four we have. Steps 1 and 2 are classical and already proven at the component level. Steps 3 through 6 are where real-world operation must prove itself. When each of the four bottlenecks passes real-load validation, the formal TRL 6-7 verification methodology applies — and that is a different document, linked below.
What We Protect — and Why That Is Normal at TRL 5-6
To make this document complete, three elements are protected as know-how at the current stage. These are not hidden facts — they are consciously undisclosed engineering specifics, standard practice in deep-tech IP strategy at the validation stage.
- The specific engineering design of the Arrester unit — including discharger construction type, internal configuration, and associated engineering choices. The patent specifies topology; the specific realization is know-how.
- The engineering realization of the primary winding (4) — its construction, geometry, and coupling parameters. The patent specifies its role in the three-circuit architecture and its resonant function with capacitor (6); the specific realization is know-how.
- The phase-alignment methodology between the three resonant circuits — specifically the engineering approach that ensures simultaneous sufficient extraction across the feedback path (secondary winding 7) and the load path (tertiary winding 10).
At TRL 5-6, before independent verification and before certification, know-how protection serves two direct functions: it preserves competitive position during the interval between validation and market entry, and it preserves the value of ongoing patent prosecution (additional filings are in progress). Expanded technical disclosure aligns with certification milestones and with qualified partner engagement under NDA. This is standard and lawful.
Patent Portfolio Anchor
- ES2950176 — granted, Spain / OEPM
- WO2024209235 — PCT, national phases active in EP, CN, IN, US
The patents describe architecture. Know-how protects realization. Validation targets operational outcome at the boundary. All three statements are simultaneously correct.